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Preliminary Data Sheet July 2001
LCK4801 Low-Voltage HSTL Differential Clock
General
The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single and multiple processor systems that require HSTL differential inputs. The LCK4801 contains a fully integrated PLL (phase-locked loop) which multiplies the HSTL_CLK or PECL_CLK input frequency to match individual processor clock frequencies. The PLL can be bypassed so that the PCLK outputs are fed from the HSTL_CLK or PECL_CLK input for test purposes. All outputs are powered from a 2 V external supply to reduce onchip power consumption. All outputs are HSTL. The PLL can operate in the internal feedback mode, or in the external feedback mode for board level debugging applications.
Features
s s s s s s
Two fully selectable clock inputs. Fully integrated PLL. 336 MHz to 1 GHz output frequencies. HSTL outputs. HSTL and LVPECL reference clocks. 32-pin TQFP package.
Description
PCLK0_EN (PULL-UP) PCLK1_EN (PULL-UP) TESTM (PULL-UP) PLLREF_EN (PULL-UP) REF_SEL (PULL-UP) 1 HSTL_CLK (PULL-UP) HSTL_CLK (PULL-UP) PECL_CLK (PULL-UP) PECL_CLK (PULL-UP) (PULL-UP) EXTFB_IN (HSTL) (PULL-DOWN) EXTFB_EN (PULL-UP) EXTFB_OUT (HSTL) SEL[4:0] (PULL-UP) RESET (PULL-UP) PLL_BYPASS (PULL-UP)
2274.a (F)
0 0 /M 1 0 1 /N PLL
0 1
PCLK0 PCLK0 (HSTL) PCLK1 PCLK1 (HSTL)
EXTFB_OUT
DECODE
Figure 1. LCK4801 Logic Diagram
LCK4801 Low-Voltage HSTL Differential Clock
Preliminary Data Sheet July 2001
Description (continued)
PLL_BYPASS PLLREF_EN
VDDHSTL
VSS RESET SEL[4] SEL[3] SEL[2] SEL[1] SEL[0] VDDA
24 25 26 27 28 29 30 31 32 1 VDDD
23
22
21
20
19
18
17 16 15 14 13 12 11 10
VDDHSTL
PCLK0
PCLK0
PCLK1
PCLK1
EXTFB_OUT EXTFB_OUT VDDHSTL EXTFB_IN EXTFB_IN EXTFB_EN PECL_CLK PECL_CLK
2 TESTM
3 VSS
4 PCLK0_EN
5 PCLK1_EN
6 REF_SEL
7 HSTL_CLK
8 HSTL_CLK
9
2275 (F)
Figure 2. 32-Pin TQFP
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Agere Systems Inc.
Preliminary Data Sheet July 2001
LCK4801 Low-Voltage HSTL Differential Clock
Pin Information
Table 1. Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name VDDD TESTM VSS PCLK0_EN PCLK1_EN REF_SEL HSTL_CLK HSTL_CLK PECL_CLK PECL_CLK EXTFB_EN EXTFB_IN EXTFB_IN VDDHSTL EXTFB_OUT EXTFB_OUT VDDHSTL PCLK1 PCLK1 PCLK0 PCLK0 VDDHSTL PLLREF_EN PLL_BYPASS VSS RESET SEL[4] SEL[3] SEL[2] SEL[1] SEL[0] VDDA I/O 1 P I G I I I I I I I I I I P O O P O O O O P I I P I I I I I I P Type Power Supply LVCMOS Ground LVCMOS LVCMOS LVCMOS Differential HSTL Differential HSTL Description 3.3 V power supply. M divider test pins. Digital ground. PCLK0 enable. PCLK1 enable. Selects the PLL input reference clock. PLL reference clock input. PLL reference clock input.
Differential LVPECL PLL reference clock input. Differential LVPECL PLL reference clock input. LVCMOS Differential HSTL Differential HSTL Power Supply Differential HSTL Differential HSTL Power Supply Differential HSTL Differential HSTL Differential HSTL Differential HSTL Power Supply LVCMOS LVCMOS Ground LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power Supply External feedback enable. External feedback input. External feedback input. Output buffers power supply. External feedback output clock. External feedback output clock. Output buffers power supply. Output clock 1. Output clock 1. Output clock 0. Output clock 0. Output buffers power supply. PLL reference enable. Input signal PLL bypass. Analog ground for PLL. PLL bypass reset (for test use). Selection of input and feedback frequency. Selection of input and feedback frequency. Selection of input and feedback frequency. Selection of input and feedback frequency. Selection of input and feedback frequency. 3.3 V filtered for PLL (PLL power supply).
1. P = power, I = input, G = ground, O = output.
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LCK4801 Low-Voltage HSTL Differential Clock
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 2. Frequency Selection Selection 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Divide M 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Feedback Divide N 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PCLK (MHz) for Given Input Frequency (MHz) 70 336 350 364 378 392 406 420 434 448 462 476 490 504 518 532 546 560 564 588 602 616 630 644 658 672 686 700 714 728 742 756 770 100 480 500 520 540 560 580 600 620 640 660 680 700 720 740 760 780 800 820 840 860 880 900 920 940 960 980 1000 NA NA NA NA NA 120 576 600 624 648 672 696 720 744 768 792 816 840 864 888 912 936 960 984 NA NA NA NA NA NA NA NA NA NA NA NA NA NA 125 600 625 650 675 700 725 750 775 800 825 850 875 900 925 950 975 1000 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
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Agere Systems Inc.
Preliminary Data Sheet July 2001
LCK4801 Low-Voltage HSTL Differential Clock
Pin Information (continued)
Table 3. Function Control Control Pin REF_SEL TESTM PLLREF_EN PLL_BYPASS EXTFB_EN PCLK0_EN PCLK1_EN RESET SEL[4:0] HSTL_CLK. M divider test mode enabled. Disable the input to the PLL and reset the M divider. Outputs fed by input reference or M divider. External feedback enabled. PCLK0 = low, PCLK0 = high. PCLK1 = low, PCLK1 = high. Resets feedback N divider. See Table 2 on page 4. 0 PECL_CLK. Reference fed to bypass MUX. Enable the input to the PLL. Outputs fed by VCO. Internal feedback enabled. PCLK0 = high, PCLK0 = low. PCLK1 = high, PCLK1 = low. Feedback enabled. See Table 2 on page 4. 1
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 4. Absolute Maximum Ratings Parameter Power Supply Input Voltage Write Current Storage Temperature Symbol VDDD/VDDA VDDHSTL VIN IIN TS Min -0.5 -0.5 -0.5 -1 -50 Typical -- -- -- -- -- Max 4.4 4.4 VDDD + 0.3 1 150 Unit V V mA C
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LCK4801 Low-Voltage HSTL Differential Clock
Preliminary Data Sheet July 2001
Electrical Characteristics
Table 5. dc Characteristics VDDA = VDDD = 3.3 V 5%, VDDHSTL = 1.7 V--2.1 V, TA = 0 C--70 C. Symbol VIH VIL VCMR VPP VIN (dc) VDIF (dc) VCM (dc) VOH VOL IDDI IDDA IDDO ThetaJA Description Input High Voltage Input Low Voltage Input High Voltage
1
Min 2.0 0.0 1 0.5 -0.3 0.4 0.4 VX + 0.3 0 -- -- -- --
Typ -- -- -- -- -- -- -- VX + 0.5 VX - 0.5 15 150 53
Max VDDD 0.8 VDDD - 0.3 1 1.45 1.75 1.0 1.4 VX - 0.3 140 20 -- --
Unit V V V V V V V V V mA mA mA C/W
Condition LVCMOS LVCMOS LVPECL LVPECL2 HSTL3 HSTL4 HSTL5 HSTL6,1 HSTL6 -- -- --7 --8
Input Low Voltage1 dc Input Signal Voltage dc Differential Input Voltage dc Common Mode Input Voltage Output High Voltage Output Low Voltage Core Supply Current PLL Supply Current Output Supply Current Junction to Ambient Thermal Resistance
1. dc levels will vary 1:1 with VDDD. 2. VPP characteristics required for ac specifications. Actual tolerance of VPP is 200 mV. 3. VIN (dc) specifies maximum dc excursion of each differential input. 4. The VDIF (dc) minimum is calculated by VOH - VOL, where VOH is the true input signal and VOL is the complementary input signal. 5. VCM specifies the maximum allowable voltage range of the input signal crosspoint. 6. VX is the differential output crosspoint voltage (see Table 6 on page 7). 7. Two PCLK signals to 25 , and one EXTFB signal through 50 . 8. 1.3 M/s (250 fpm) airflow.
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Agere Systems Inc.
Preliminary Data Sheet July 2001
LCK4801 Low-Voltage HSTL Differential Clock
Electrical Characteristics (continued)
Table 6. ac Characteristics VDDA = VDDD = 3.3 V 5%, VDDHSTL = 1.7 V--2.1 V, TA = 0 C--70 C. Symbol fref fMAX tsk (o) tjit (0) tjit (cc) Description Input Frequency Maximum Output Frequency Skew Error (PCLK) Phase Jitter (I/O Jitter) Cycle-to-Cycle Jitter (Full Period) Min -- 336 -- -- -- -- 0.6 0.68 -- Typ 70--125 -- -- -- -- -- -- -- -- Max -- 1000 35 (output period)/2 5 8 -- 0.9 10 Unit MHz MHZ ps -- % % V V ms Condition -- --1 --2 --2 --2,3 --2,4 For all HSTL output pairs. For all HSTL output pairs. --
tjit (1/2 period) Cycle-to-Cycle Jitter (Half Period) VDIFout VX tlock Differential Output Peak-to-Peak Swing Differential Output Crosspoint Voltage Maximum PLL Lock Time
1. When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtained from PECL input. 2. At differential pair crossover. 3. Full PCLK period. 4. Half PCLK period.
VDDHSTL VOH VDIF VX VCM VOL VSS
2276 (F)
Figure 3. HSTL Differential Input Levels
Z = 50
OUTPUT RT = 25 VTT = VSS (GROUND)
2277 (F)
Figure 4. Output Termination and ac Test Reference
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LCK4801 Low-Voltage HSTL Differential Clock
Preliminary Data Sheet July 2001
Applications
Power Supply Filtering
The LCK4801 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being when this noise is seen on the power supply pins. The LCK4801 provides separate power supplies for the output buffers (VDDHSTL) and the phase-locked loop (VDDA) of the device in order to isolate the high digital output switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is adequate. However, in a digital system, a second level of isolation is suggested. The easiest way to accomplish this is to add a power supply filter on the VDDA pin of the LCK4801. Figure 5 on page 9 shows the typical power supply scheme. The filter should be designed in the 10 kHz--1 MHz range, since this is the most likely frequency range to cause spectral content noise. Note the dc voltage drop between VDDD and VDDA on the power supply filter. Very little dc voltage drop can be tolerated when a 3.3 V VDDD supply is used. The power supply filter in Figure 5 must be 5 --10 in order to meet the drop criteria. The RC filter in Figure 5 will provide a broadband filter with approximately 100:1 attenuation above 20 kHz. The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.
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Agere Systems Inc.
Preliminary Data Sheet July 2001
LCK4801 Low-Voltage HSTL Differential Clock
Applications (continued)
3.3 V RS = 5--10 VDDA 0.01 F
22 F
VDDD 0.01 F
2278 (F)
Figure 5. Power Supply Filter Although the LCK4801 has an isolated power supply and grounds, as well as fully differential PLL, there still may be applications in which overall performance is being compromised due to system power supply noise. The power supply filter schemes discussed are adequate to eliminate power supply noise problems in most designs.
Agere Systems Inc.
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LCK4801 Low-Voltage HSTL Differential Clock
Preliminary Data Sheet July 2001
Outline Diagram
Dimensions are in millimeters.
9.00 0.20 7.00 0.20 PIN #1 IDENTIFIER ZONE
32 25
1.00 REF
0.25 GAGE PLANE
1 24
SEATING PLANE 0.45/0.75 7.00 0.20 9.00 0.20
DETAIL A
8
17
9
16
0.09/0.200
DETAIL A
DETAIL B 1.40 0.05
0.30/0.45 0.20
M
1.60 MAX SEATING PLANE 0.10 0.80 TYP 0.05/0.15
DETAIL B
12-3076(F)
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A.
July 2001 DS01-234HSI

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